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MP1907 100v, 2.5a, high frequency half-bridge gate driver MP1907 rev. 1. 1 www.monolithicpower.com 1 11/20/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. the future of analog ic technology descri ption the mp190 7 is a h i gh frequency, 100v half bridge n-channel power mosfet d r iver. its low side and high side driver c hannels ar e independent ly controlled and match ed with le ss than 5ns in time delay. under-volt age lock-ou t both high side and low side supplie s force their outputs low in case of insufficie n t supply. both outputs will remain low until a rising edge on either inpu t is dete c ted. the integrated bootstrap d i ode reduces external component count. features ? drives n-channel mosfet half bridge ? 100v v bst voltage range ? input signal overlap protection ? on-chip bootstrap diode ? typical 20n s propagatio n delay time ? less than 5 ns gate drive mismatch ? drive 1nf l oad with 12ns/9ns rise/f all times with 12v vdd ? ttl compatible input ? less than 1 5 0 a quiescent current ? less than 5 a shutdo wn curre n t ? uvlo for bo th high side and low side ? in 33mm qfn10 packages appli c ations ? battery powered hand tool ? telecom half bridge power supplies ? avionics dc-dc convert e rs ? active-clamp forward converters a l l m ps pa rts a r e lea d - fr ee an d a d h e r e to t h e ro hs di rect i v e . f o r m p s g r e e n sta t u s , plea se v i sit mps w ebsite under produ cts, quali t y assuran c e page. ?mp s ? a n d ?t he fu ture o f a n a l og ic te ch no lo gy ? a r e re gi stere d tra dem ar ks o f monolithic power systems, inc. typical application mi c r o c ont r o l l er 3. 3v batt control fl o a t i ng dr i v e r lo w -side driver m m p 19 07 in h in l en vd d bs t drv h sw drv l 13 4 5 10 9 7 6 8 vss http://
MP1907 D 1 00v, 2.5a, high f r equenc y ha lf-brid g e gate dri ver MP1907 rev. 1. 1 www.monolithicpower.com 2 11/20/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. ordering information part number* package top marking MP1907gq qfn10 (3 x 3 mm) abn * for tape & reel, add suffix ?z (e.g. MP1907gq?z); package reference absolute m a xi mum ratings (1) supply voltage (v dd ) ..................... -0.3v to +20v sw voltage (v sw ) ......................... -5.0v to 105v bst voltage (v bst ) ....................... -0.3v to 110v bst to sw .................................... -0.3v to +18v drvh to sw .............. -0.3v to (bst-sw) +0.3v drvl to vss ...................... -0.3v to (v dd +0.3v) all other pins .................................. -0.3v to 20v continuous power dissipation (t a =+25c) (2) qfn10 (3x3 ) .............................................. 2.5w junction te mperature ............................... 150 c lead temperature .................................... 260 c storage temperature ............... -65c to +150 c recommended operating conditions (3) supply voltage (v dd ) ................. +4.5v to 18v (4) sw voltage (v sw ) ......................... -1.0v to 100v sw slew rate ...................................... <50v/nsec operating junction temp. (t j ). -40c to +125c thermal resistance (5) ja jc qfn10 (3x3 ) ........................... 50 ...... 12 ... c/w notes : 1) exceeding these ratings ma y da m age the device. 2) the ma ximum allowable po w e r dissipation is a fun c tion of the max i mum juncti on tempe r atu r e t j (max ), th e junction-to- ambient therm a l resistance ja , a nd the am bient t e mperatu r e t a . the m a ximu m allow a ble con t inuous po w e r dissipation at an y ambient te mperatu r e is calculated b y p d (max) = (t j (max)-t a )/ ja . exceeding the maximum allo wable po w e r dissipation w ill cause ex cessive die temperature, and th e regulator w ill go into thermal shutdo w n . inte rnal thermal shutdo w n circuitr y protects t h e device from perma nent damage. 3) the device is not guarant eed to function outside of its operating conditions. 4) 4.5v is only a t y pical value for minimum suppl y vo ltage at v dd falling 5) measured on jesd51-7, 4-layer pcb.
MP1907 D 1 00v, 2.5a, high f r equenc y ha lf-brid g e gate dri ver MP1907 rev. 1. 1 www.monolithicpower.com 3 11/20/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. electri c al characteristi cs v dd = v bst -v sw =12v, v ss =v sw = 0v, v en =3.3 v, no load at drvh and drvl, t a = + 2 5 c, unless otherw i se n o ted. parameter symbol condition min typ max units supply current vdd shutd o w n current i shdn v en =0, 0 1 a vdd qui esce nt current i ddq inl=i n h=0 80 100 a vdd op eratin g curre n t i ddo fsw=50 0khz 2.8 3.5 ma floating d r ive r quie s cent current i bst q inl=0, inh=0 or 1 55 70 a floating d r ive r ope rating cu rre nt i bst o fsw=50 0khz 2.1 3 ma leakage current i lk bst=sw=100v 0.05 1 a inputs inl/inh high 2.4 v inl/inh low 1 v inl/inh hyst ere s is 0.6 v inl/inh internal pull-down resi st an ce r in 185 k under voltage protection vdd rising threshold v ddr 4.6 5.0 5.4 v vdd falling threshold v ddf 4.1 4.5 4.9 v (bst-sw) rising threshold v bstr 4.6 5.0 5.4 v (bst-sw) falling threshold v bstf 4.1 4.5 4.9 v en input logi c lo w 0.7 v en input logi c hig h 1.5 v en hyste r e s i s 100 mv en input cu rrent i en v en =2v 10 a en intern al p u ll-do wn re sistance r en 200 k bootstrap diode bootstra p dio de vf @ 10 0 u a v f1 0.55 v bootstra p dio de vf @ 10 0 m a v f2 1 v bootstra p dio de dynami c r r d @ 100 ma 2.7 low side gate driver low level o u tput voltage v oll i o =100ma 0.15 0.22 v high level output voltage to rail v ohl i o =-100ma 0.45 0.6 v v drvl =0v , v dd =4. 5 v (7) 0.15 a v drvl =0v , v dd =12v 1.5 a peak pull - u p curre n t (6) i ohl v drvl =0v , v dd =16v 2.5 a v drvl =v dd =4. 5 v (7) 0.25 a v drvl =v dd =12v 2.5 a peak pull - d o w n current (6) i oll v drvl =v dd =16v 3.5 a floating gate driver low level o u tput voltage v olh i o =100ma 0.15 0.22 v
MP1907 D 1 00v, 2.5a, high f r equenc y ha lf-brid g e gate dri ver MP1907 rev. 1. 1 www.monolithicpower.com 4 11/20/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. electri c al characteristi cs (continued) v dd = v bst -v sw =12v, v ss =v sw = 0v, v en =3.3 v, no load at drvh and drvl, t a = + 2 5 c, unless otherw i se n o ted. parameter sy mbol conditio n min t y p max units high level out put voltage to rail v ohh i o =-10 0ma 0.45 0.6 v v drvh =0v , v bst - v sw =5v (8) 0.25 a v drvh =0v , v dd =12v 1.5 a peak pull - u p curre n t (6) i ohh v drvh =0v , v dd =16v 2.5 a v drvh =v bst - v sw =5v (8) 0.65 a v drvh =v dd =12v 2.5 a peak pull - d o w n current (6) i olh v drvh =v dd =16v 3.5 a switching spec. --- low side gate driver turn -off pro p agation d e lay inl falling to drvl falling t dlff 20 ns turn -on p r o p agation d e lay inl risi ng to drvl risi ng t dlrr 20 ns drvl ris e time c l =1 nf 12 ns drvl fall time c l =1 nf 9 ns switching spec. --- floating gate driver turn -off pro p agation d e lay inl falling to drv h falling t dhff 20 ns turn -on p r o p agation d e lay inl risi ng to drv h ri sing t dhrr 18 ns drv h ri se time c l =1 nf 12 ns drv h fall time c l =1 nf 9 ns switching spec. --- matching floating d r ive r turn -off to low side drive turn -on t mo n 1 5 ns low si de driv er turn -off to floating driver turn-on t mo f f 1 5 ns minimum inp u t pulse wid t h that cha nge s the output t pw 50 (6) ns bootstra p dio de turn -on or turn-off time t bs 10 (6) ns note: 6) guar anteed b y d e sign. 7) after startup v dd fall to 4.5v 8) after startup v bst - v sw fa ll to 5v input (inh, inl) output (dr v h, drvl ) t d hrr , t dl rr t dh f f , t dlf f in pu t (i n h , i n l) ou tp u t (dr v h, drvl ) t d hrr , t dl rr t dhff , t dlff in l in h dr vl dr vh t mo n t mo f f figure 1?timing diagram
MP1907 D 1 00v, 2.5a, high f r equenc y ha lf-brid g e gate dri ver MP1907 rev. 1. 1 www.monolithicpower.com 5 11/20/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. pin functio n s packag e pin # name description 1 vdd supply input. this pin su p p lies po we r to all the internal circuitry. a decou pling capa citor t o ground must be placed close to this pin to ensure stable and clean supply. 2 nc no connection. 3 bst bootstra p. this is the positive powe r sup p ly for th e internal floating high-si de mosfet driver. connect a bypass capacito r between this pin and sw pin. 4 drvh floating driver output. 5 sw switching node. 6 en on/off control. 7 inh control signal input for the floating driver. 8 inl control signal input for the low side driver. 9 vss, exposed pad chip ground. connect to exposed pad to vss for proper thermal operation. 10 drvl low side driver output.
MP1907 D 1 00v, 2.5a, high f r equenc y ha lf-brid g e gate dri ver MP1907 rev. 1. 1 www.monolithicpower.com 6 11/20/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. typical performance characteristics v dd =12v, v ss =v sw = 0v, t a = +25 c, unless otherwise noted. i ddo o p e ra t i o n curre nt v s . f re q ue ncy 0 1 2 3 4 5 6 0 200 400 600 800 1000 i bst o o p e ra t i o n curre nt v s . fr e q u e n c y 0 1 2 3 4 0 200 400 600 800 1000 high lev e l o u tp u t v o l t a g e v s . t e m p e rat ure v oh l ,v oh h (v) low level o u tp u t v o lta g e v s. t e m p e rat ure v ol l ,v ol h (v) undervolt a g e l o c ko ut t hre s ho l d v s . t e m p e r a t u r e v bs t r ,v ddr (v) undervolta g e l o ck o u t h y st e r e s i s v s . t e m p e rat ure v bsth ,v ddh (mv) t=0 o c prop a ga t ion d e l a y v s . t emper a t u r e 13 14 15 16 17 18 19 20 - 50 0 50 100 150 t dhrr t dl rr t dl f f t dhff boo t s t ra p di o de i - v ch ar act e r i s t i cs 0. 0001 0. 001 0. 01 0. 1 1 0. 5 0. 6 0. 7 0. 8 0. 9 1 f o rw ard v o l t a g e (v ) f o rw ard curre n t (a) q u i e sce n t curre n t v s. v olta g e v dd ,v bs t (v ) -50 0 50 100 150 -5 0 0 50 100 150 4. 92 4.94 4. 96 4. 98 5. 00 5. 02 5. 04 5. 06 5. 08 5. 10 - 50 0 50 100 150 450 460 470 480 490 500 510 - 50 0 50 100 150 10 20 30 40 50 60 70 80 90 048 1 2 1 6 2 0 v bstr v ddr v bsth v ddh i ddq vs. v dd i bstq vs. v bst 0. 00 0. 05 0. 10 0.15 0. 20 0. 25 0. 30 0. 35 0. 40 0. 45 0. 50 0. 00 0. 05 0. 10 0. 15 0. 20 0. 25 0. 30 0. 35 0. 40 0. 45 0. 50 v bst =v dd =12v v bst =v dd =12v
MP1907 D 1 00v, 2.5a, high f r equenc y ha lf-brid g e gate dri ver MP1907 rev. 1. 1 www.monolithicpower.com 7 11/20/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. typical performanc e characteristics (continued) v dd =12v, v ss =v sw = 0v, t a = +25 c, unless otherwise noted. v dd (v) p eak c u r r en t vs. v dd vo l t a g e 0 0. 5 1 1. 5 2 2. 5 3 3. 5 4 8 1 01 21 41 61 82 0 p eak c u r r en t ( a ) i oll i olh i ohh i ohl
MP1907 D 1 00v, 2.5a, high f r equenc y ha lf-brid g e gate dri ver MP1907 rev. 1. 1 www.monolithicpower.com 8 11/20/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. typical performanc e characteristics (continued) v dd =12v, v ss =v sw = 0v, t a = +25 c, unless otherwise noted. inh 2v/div . drvh 5v/div. turn-on propagation delay inl 2v/div . drvl 5v/div. turn-on propagation delay drvh 5v/div. drive rise time (1nf load) drvl 5v/div. drive rise time (1nf load) drvh 5v/div. drive fall time (1nf load) drvl 5v/div. drive fall time (1nf load) inl & inh 5v/div . dr vl 10v/div . drvh 10v/div. input signal overlap protection 20ns 20ns 12ns 8ns 5.2ns 5.2ns iinh 2v/div . drvh 5v/div. turn-off protection delay inl 2v/div . drvl 5v/div. turn-off protection delay 18ns 18ns
MP1907 D 1 00v, 2.5a, high f r equenc y ha lf-brid g e gate dri ver MP1907 rev. 1. 1 www.monolithicpower.com 9 11/20/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. typical perfo r manc e characteristics (c ontinued) v dd =5v, after startup v dd falls to 5v, v ss =v sw = 0v, t a = +25 c, unless otherwise noted. i ddo o p e ra t i o n curre nt v s . f re q ue ncy freq u en cy ( kh z ) f r eq u en cy ( kh z ) i bsto o p e ra t i o n curre nt v s . fr e q u e n c y v bst - v sw =5v h i g h level output voltage vs.temperature v oh l ,v oh h (v) low level outpu t v o lta g e v s. t e m p e rat ure v ol l ,v ol h (v ) propagation d e l a y v s . t em per a t u r e 0.0 0.2 0. 4 0. 6 0. 8 1. 0 0 200 400 600 800 1000 0. 0 0. 2 0. 4 0. 6 0. 8 0 200 400 600 8 00 1000 0. 0 0. 2 0. 4 0.6 0.8 1. 0 1. 2 - 5 0 0 50 100 150 0. 00 0. 05 0. 10 0. 15 0. 20 0. 25 0. 30 0. 35 0. 40 - 5 0 0 50 100 150 20 25 30 35 40 45 - 50 0 50 100 150 v bst =v dd =5v v bst =v dd =5v t dl rr t dlf f
MP1907 D 1 00v, 2.5a, high f r equenc y ha lf-brid g e gate dri ver MP1907 rev. 1. 1 www.monolithicpower.com 10 11/20/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. typical perfo r manc e characteristics (c ontinued) v dd =5v, after startup v dd falls to 5v, v ss =v sw = 0v, t a = +25 c, unless otherwise noted. inl 2v/div . drvl 2v/div. turn-on propagation delay drvl 2v/div. drive rise time (1nf load) inl 2v/div . drvl 2v/div. turn-off propagation delay drive fall t ime (1nf load) drvl 2v/div. 28ns 20ns 30ns 8ns
MP1907 D 1 00v, 2.5a, high f r equenc y ha lf-brid g e gate dri ver MP1907 rev. 1. 1 www.monolithicpower.com 11 11/20/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. block diagram figure 2?function block diagram
MP1907 D 1 00v, 2.5a, high f r equenc y ha lf-brid g e gate dri ver MP1907 rev. 1. 1 www.monolithicpower.com 12 11/20/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. operation sw itch sho o t-through protection the input signals of inh and inl a r e controlled independent ly. input shoot-through protectio n circuitry is implemented to pre v ent shoot- through be tween the hsfet and lsfet outputs. only one of the fet drivers can be on at one time. if both inh and inl are high at the same time, both hsfet and lsfet will be off. under voltage lock out when vdd or bst goes below their respective uvlo thre sholds, bot h drvh and drvl outputs will go low to tu rn off both fets. once vdd rises above the uvlo threshold, both drvh and drvl will stay low until a risin g edge is dete c ted on eith er inh or inl. the truth ta ble in table 1 details th e operation of the hsfet and lsfet under different inh, inl and uvlo conditio n s table1 states of driver output under different conditions en bst-s w voltage v dd voltage inh i nl drv h drvl uvlo la tch sta t us opera t ing conditio n 0 x x x x open 200 k ? pull do wn x x x x 0 0 0 0 x x x 1 1 0 0 x x above uvlo 0 1 0 1 normal above uvlo above uvlo 1 0 1 0 normal normal op eration falls bel ow uvlo above uvlo x x 0 0 normal to tripp ed above uvlo falls bel ow uvlo x x 0 0 normal to tripp ed normal-to - t r i pped tran sition x above uvlo 0 or 1 0 or 1 0 0 tripp ed x below uv lo x x 0 0 tripp ed when uvlo latc h is tripped. x above uvlo 0 to 1 0 to 1 0 0 tripp ed, re set by inl & inh x above uvlo 1 to 0 1 0 0 to 1 tripp ed, re set by inh falling below uvlo above uvlo 1 1 to 0 0 0 tripp ed, re set by inl falling above uvlo above uvlo 1 1 to 0 0 to 1 0 tripp ed, re set by inl falling below uvlo above uvlo 0 0 to 1 0 0 to 1 tripp ed, re set by inl below uvlo above uvlo 0 to 1 0 0 0 tripp ed, re set by inh 1 above uvlo above uvlo 0 to 1 0 0 to 1 0 tripp ed, re set by inh tripp ed to no rmal tran sition note: x = don?t c are. .
MP1907 D 1 00v, 2.5a, high f r equenc y ha lf-brid g e gate dri ver MP1907 rev. 1. 1 www.monolithicpower.com 13 11/20/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. appli c ation information reference design circuits half bridge motor driv er t in half - bridge co nverter topology, the mosfets are driven alt e rnately with some dea d time. therefore, inh and inl are driven with alternating signals from the pwm controller. th e input voltage can be up to 100v in this application . en in h in l vss dr v l sw dr v h bst nc vdd drvl drvl 1 2 3 4 5 10 9 8 7 6 en in h in l u p to 1 0 0 v m vd d 4. 5v t o 1 8v 10 f + MP1907 figure 3?half-bridge motor driv er
MP1907 D 1 00v, 2.5a, high f r equenc y ha lf-brid g e gate dri ver MP1907 rev. 1. 1 www.monolithicpower.com 14 11/20/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. active-cla m p forw a r d converte r in active-cla mp forward converter t opology, the mosfets are driven alternately. the high-side mosfet, along with capacitor c re set , is used to reset the po wer transformer in a lossless mann er. this topolo g y lends it self well to run at dut y cycles exce eding 50%. for the s e reasons, th e input voltage may not b e able to ru n at 100v for this application. en in h in l vs s dr v l sw drv h bs t nc vdd drvl drvl 1 2 3 4 5 10 9 8 7 6 en in h in l up t o 1 0 0 v vd d 9v t o 1 8 v 10f + MP1907 secondary circuit + cr e s e t figure 4?active-clamp forw a r d converte r
MP1907 D 1 00v, 2.5a, high f r equenc y ha lf-brid g e gate dri ver notice: t he i n formatio n in this docum ent is subject to chang e w i t h o u t notice. please c ontact m ps for current specifi c ations. users sho u ld w a rrant a nd g u a rante e that thi r d part y inte lle ctual prop ert y rights ar e n o t infring ed u pon w h e n inte grati ng mps prod ucts into a n y app licati on. mps w i ll n o t assume an y l e g a l resp onsi b il ity for an y sa id a pplic atio ns. MP1907 rev. 1. 1 www.monol i t hi cpower.com 15 11/20/2013 mps propri e tar y informati on. pate nt protec ted. un authori z ed photo c op y and d upl i c ati on prohi bi ted. ? 2013 mps. al l ri ghts reserved. package informati o n qfn10 (3 3 mm) side view top view 1 10 6 5 bottom view 2.90 3.10 1.45 1.75 2.90 3.10 2.25 2.55 0.50 bsc 0.18 0.30 0.80 1.00 0.00 0.05 0.20 ref pin 1 id mark ing 1.70 0.50 0.25 recommended land pattern 2.90 note : 1) a l l dimensions ar e in millimeters. 2) exposed paddle size does not include mold flash. 3) l e ad c o pl ana rity sh all be 0.10 mill imeter ma x. 4) d rawing conforms to jed e c mo-229, v a riation veed-5 . 5) drawing is not to scale. pin 1 id see detail a 2.50 0.70 pin 1 id option b r0.20 typ. pin 1 id option a r0.20 typ. detail a 0.30 0.50 pin 1 id index area

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